base_system Project Status (10/14/2015 - 12:48:04)
Project File: axi_timer_test.xise Parser Errors: No Errors
Module Name: base_system Implementation State: Programming File Not Generated
Target Device: xc6slx9-2csg324
  • Errors:
  
Product Version:ISE 14.7
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment:  
  • Final Timing Score:
   
 
XPS Reports [-]
Report NameGenerated ErrorsWarningsInfos
Platgen Log File 10 14 12:36:08 201501 Warning (1 new)11 Infos (0 new)
Simgen Log File    
BitInit Log File 10 14 12:48:03 20150011 Infos (0 new)
System Log File    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrent 10 14 12:47:54 2015

Date Generated: 10/14/2015 - 12:48:04